Subsystem

Global functionality

The CVA6 is a subsystem composed of the modules and protocol interfaces as illustrated The processor is a Harvard-based modern architecture. Instructions are issued in-order through the DECODE stage and executed out-of-order but committed in-order. The processor is Single issue, that means that at maximum one instruction per cycle can be issued to the EXECUTE stage.

The CVA6 implements a 6-stage pipeline composed of PC Generation, Instruction Fetch, Instruction Decode, Issue stage, Execute stage and Commit stage. At least 6 cycles are needed to execute one instruction.

Connection with other sub-systems

The submodule is connected to :

• NOC interconnect provides memory content

• COPROCESSOR connects through CV-X-IF coprocessor interface protocol

• TRACER provides support for verification

• TRAP provides traps inputs

Parameter configuration

cv32a65x parameter configuration

Name	description	Value
XLEN	General Purpose Register Size (in bits)	32
FPGA_EN	Is FPGA optimization of CV32A6	0
NrCommitPorts	Number of commit ports	1
AxiAddrWidth	AXI address width	64
AxiDataWidth	AXI data width	64
AxiIdWidth	AXI ID width	4
AxiUserWidth	AXI User width	32
MemTidWidth	TODO	2
NrLoadBufEntries	Load buffer entry buffer	1
FpuEn	Floating Point	0
XF16	Non standard 16bits Floating Point	0
XF16ALT	Non standard 16bits Floating Point Alt	0
XF8	Non standard 8bits Floating Point	0
RVA	Atomic RISC-V extension	0
RVB	Bit manipulation RISC-V extension	1
RVV	Vector RISC-V extension	0
RVC	Compress RISC-V extension	1
RVZCB	Zcb RISC-V extension	1
RVZCMP	Zcmp RISC-V extension	0
XFVec	Non standard Vector Floating Point	0
CvxifEn	CV-X-IF coprocessor interface is supported	1
ZiCondExtEn	Zicond RISC-V extension	0
RVS	Supervisor mode	0
RVU	User mode	0
NrScoreboardEntries	Scoreboard length	4
HaltAddress	Address to jump when halt request	64’h800
ExceptionAddress	Address to jump when exception	64’h808
RASDepth	Return address stack depth	2
BTBEntries	Branch target buffer entries	0
BHTEntries	Branch history entries	32
DmBaseAddress	Base address of the debug module	64’h0
TvalEn	Tval Support Enable	0
NrPMPEntries	Number of PMP entries	8
PMPCfgRstVal	PMP CSR configuration reset values	{16{64’h0}}
PMPAddrRstVal	PMP CSR address reset values	{16{64’h0}}
PMPEntryReadOnly	PMP CSR read-only bits	16’d0
NOCType	NOC bus type	config_pkg::NOC_TYPE_AXI4_ATOP
NrNonIdempotentRules	Number of PMA non idempotent rules	2
NonIdempotentAddrBase	PMA NonIdempotent region base address	{64’b0 64’b0}
NonIdempotentLength	PMA NonIdempotent region length	{64’b0 64’b0}
NrExecuteRegionRules	Number of PMA regions with execute rules	3
ExecuteRegionAddrBase	PMA Execute region base address	{64’h8000_0000 64’h1_0000 64’h0}
ExecuteRegionLength	PMA Execute region address base	{64’h40000000 64’h10000 64’h1000}
NrCachedRegionRules	Number of PMA regions with cache rules	1
CachedRegionAddrBase	PMA cache region base address	{64’h8000_0000}
CachedRegionLength	PMA cache region rules	{64’h40000000}
MaxOutstandingStores	Maximum number of outstanding stores	7
DebugEn	Debug support	0
AxiBurstWriteEn	AXI burst in write	0
IcacheByteSize	Instruction cache size (in bytes)	2048
IcacheSetAssoc	Instruction cache associativity (number of ways)	2
IcacheLineWidth	Instruction line width	128
DcacheByteSize	Data cache size (in bytes)	32768
DcacheSetAssoc	Data cache associativity (number of ways)	8
DcacheLineWidth	Data line width	128
DataUserEn	TODO	0
FetchUserWidth	TODO	32
FetchUserEn	TODO	0

IO ports

cva6 module IO ports

Signal	IO	Description	connexion	Type
clk_i	in	Subsystem Clock	SUBSYSTEM	logic
rst_ni	in	Asynchronous reset active low	SUBSYSTEM	logic
boot_addr_i	in	Reset boot address	SUBSYSTEM	logic[CVA6Cfg.VLEN-1:0]
hart_id_i	in	Hard ID reflected as CSR	SUBSYSTEM	logic[CVA6Cfg.XLEN-1:0]
irq_i	in	Level sensitive (async) interrupts	SUBSYSTEM	logic[1:0]
ipi_i	in	Inter-processor (async) interrupt	SUBSYSTEM	logic
time_irq_i	in	Timer (async) interrupt	SUBSYSTEM	logic
cvxif_req_o	out	CVXIF request	SUBSYSTEM	cvxif_req_t
cvxif_resp_i	in	CVXIF response	SUBSYSTEM	cvxif_resp_t
noc_req_o	out	noc request, can be AXI or OpenPiton	SUBSYSTEM	noc_req_t
noc_resp_i	in	noc response, can be AXI or OpenPiton	SUBSYSTEM	noc_resp_t

Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below

As DebugEn = 0,

debug_req_i input is tied to 0

As IsRVFI = 0,

rvfi_probes_o output is tied to 0